Importance of High-Tech Facility
The driving of semiconductor will reach the manufacturing processes for the chips of 2 nm and Intelligent heterogeneous integration soon. The driving is an inevitable trend to bring forth improved knowledge, technology, economy, and quality of life in Taiwan. To advance semiconductor technology, designing/ building/certifying/transferring the facility to users is part of and prerequisite to semiconductor Research, Development and Manufacturing (R&D&M.)
Therefore, it is important to enhance the scientific and technologic level of semiconductor facility research for further advancing semiconductor R&D&M of Taiwan. High performance tools, extremely delicate R&D instruments, and ultra pure utilities are needed for advanced semiconductor R&D&M. However, these tools/instruments/utilities must be housed in stringently controlled cleanrooms, operated on stable platforms, and/or performed under an electromagnetic interference.
In addition, to sustain the global competitiveness of Taiwan semiconductor industry and to cope with the new challenges in the coming era of Intelligent heterogeneous integration chips production and 2~1 nanometer of manufacturing process, there is an imminent need to enhance the efficiency of design and construction of fabrication plants (fab) and to ensure high quality of the production environment in Taiwan.
Moreover, because of the extremely controlled environment needed for wafer production, semiconductor fab consumes a lot of energy and generates carbon dioxide that affects global warming and ecosystems. To optimize the energy consumption and to minimize the carbon dioxide through real-time intelligent monitoring become inevitable challenging in the coming years.
However, development of the related technologies in the areas of stable platform, electromagnetic free space, ultrapure air cleanroom, energy saving and reduction of carbon dioxide is a complex processes involving many considerations, not typically dealt by an individual discipline. This demands an interdisciplinary approach to collectively resolve the issues with industrial experts. Hopefully, through this collaborative research not only put Taiwan on the upfront research in semiconductor facility R&D.
Therefore, it is important to enhance the scientific and technologic level of semiconductor facility research for further advancing semiconductor R&D&M of Taiwan. High performance tools, extremely delicate R&D instruments, and ultra pure utilities are needed for advanced semiconductor R&D&M. However, these tools/instruments/utilities must be housed in stringently controlled cleanrooms, operated on stable platforms, and/or performed under an electromagnetic interference.
In addition, to sustain the global competitiveness of Taiwan semiconductor industry and to cope with the new challenges in the coming era of Intelligent heterogeneous integration chips production and 2~1 nanometer of manufacturing process, there is an imminent need to enhance the efficiency of design and construction of fabrication plants (fab) and to ensure high quality of the production environment in Taiwan.
Moreover, because of the extremely controlled environment needed for wafer production, semiconductor fab consumes a lot of energy and generates carbon dioxide that affects global warming and ecosystems. To optimize the energy consumption and to minimize the carbon dioxide through real-time intelligent monitoring become inevitable challenging in the coming years.
However, development of the related technologies in the areas of stable platform, electromagnetic free space, ultrapure air cleanroom, energy saving and reduction of carbon dioxide is a complex processes involving many considerations, not typically dealt by an individual discipline. This demands an interdisciplinary approach to collectively resolve the issues with industrial experts. Hopefully, through this collaborative research not only put Taiwan on the upfront research in semiconductor facility R&D.
由於半導體產業在台灣的大幅發展，不但提升了台灣在國際間的競爭力，促使台灣其他產業技術升級，且帶領台灣地區經濟成長。如此，不僅是對台灣經濟發展有深遠的影響，同時也使得台灣擁有卓越的國際科技地位。根據多方之報導，國際半導體及相關產業將於2025年全面進入2 奈米 (Gate Length)，及智慧異質整合晶片 (intelligent heterogeneous integration chips) 之製程技術，廠房從施工興建至開始裝設生產設備，將於12~18個月內完成。
但要推進提昇台灣半導體製程技術的到2奈米及智慧異質整合，廠房和實驗室等設施之設計、建造、驗證、完成及轉移使用，是半導體研發製造提昇中一個不可或缺的先決條件。
而廠房設施之研發亦是半導體產業研發製造不可或缺的重要環節。提升台灣半導體之製程技術，廠房設施之研發亦應積極配合，不可等閒視之，必須未雨綢繆加速研發。半導體之研發製造過程中，對於環境控制的要求甚為嚴格，隨著製程閘寬(Gate Length) 愈來愈小，晶圓愈來愈大，廠房設施之興建是愈來愈快，投資金額愈來愈高，廠房設施之要求亦愈來愈高。
由於半導體對台灣經濟愈來愈重要，而半導體研發製造必須在嚴格控制的潔淨室中，因此提昇半導體廠房設施之等級為目前相當重要之課題。根據台灣經濟部統計處之報告(Statistics Division of the Ministry of Economic Affairs) ，112年台灣12吋晶圓產值達兩兆兩千一百八十一億元: https://m.cnyes.com/news/id/5515190
但要推進提昇台灣半導體製程技術的到2奈米及智慧異質整合，廠房和實驗室等設施之設計、建造、驗證、完成及轉移使用，是半導體研發製造提昇中一個不可或缺的先決條件。
而廠房設施之研發亦是半導體產業研發製造不可或缺的重要環節。提升台灣半導體之製程技術，廠房設施之研發亦應積極配合，不可等閒視之，必須未雨綢繆加速研發。半導體之研發製造過程中，對於環境控制的要求甚為嚴格，隨著製程閘寬(Gate Length) 愈來愈小，晶圓愈來愈大，廠房設施之興建是愈來愈快，投資金額愈來愈高，廠房設施之要求亦愈來愈高。
由於半導體對台灣經濟愈來愈重要，而半導體研發製造必須在嚴格控制的潔淨室中，因此提昇半導體廠房設施之等級為目前相當重要之課題。根據台灣經濟部統計處之報告(Statistics Division of the Ministry of Economic Affairs) ，112年台灣12吋晶圓產值達兩兆兩千一百八十一億元: https://m.cnyes.com/news/id/5515190
The Role of Civil Engineering in Semiconductor Chips Manufacturing [1、2、5、6]：
It is well understood that in the era of rapid technological advancement, semiconductors are the backbone of all high-tech industries. The chips produced using these semiconductors integrate intricate software programs and ultimately drive the high-tech devices we use, such as robots, the Internet of Things (IoT), big data, cloud computing, virtual reality (VR,) artificial intelligence (AI) and quantum computing.
In the complex manufacturing and further development processes of high-tech semiconductor chips, the use of high-performance manufacturing equipment, precision instruments, and ultra-pure water, electricity, air, and chemicals are necessary. These facilities must be hosted in cleanrooms with tightly controlled environments for ensuring stable manufacturing conditions free from vibration interference.
These sophisticated equipment and precision instruments must be installed on stable structural platforms provided by civil engineering. This includes addressing vibrations arising from earthquakes, noise, electromagnetic interference (EMI), radio frequency (RF) interference, airflow, and machine resonance, all of which require the expertise of structural and geotechnical engineers.
Moreover, the purification of water, air, and chemicals needed for production and the treatment and recycling of wastewater, exhaust gases, and waste chemicals involve energy conservation and carbon reduction, tying directly into the domain of civil engineering's hydraulic and environmental engineering.
In the new generation of unmanned high-tech semiconductor manufacturing, the processes might involve hundreds of steps. The transportation of materials and products between machines requires an optimized automated material handling system (AMHS), involving route selection and queuing optimization, which also falls under the purview of civil engineering's transportation engineering.
Furthermore, with advancements in nanotechnology, it's been discovered that particles at the nano-scale exhibit properties significantly different from their larger material counterparts. As these particles decrease in size, their surface area-to-volume ratio increases, which significantly affects their chemical and physical behaviors. This change impacts the material's color, surface reactivity, optical properties, magnetic
properties, mechanical strength, thermal behavior, catalytic activity, or biocompatibility. With semiconductor transistor line widths now entering processes below 2 nanometers, the urgent application of advanced nano-materials in civil engineering is a pressing matter.
Moreover, the construction and operation of high-tech semiconductor chips manufacturing facilities demand stringent spatial information requirements. The precise and defined spatial engineering provided by civil engineering is crucial for the successful execution of these projects. Surveyors and geospatial engineers in civil engineering discipline are duty bound.
Additionally, a high-tech semiconductor manufacturing facility, particularly those with advanced processing capabilities, may cost between one to three trillion Taiwanese dollars (approximately 30 to 90 billion USD), with construction personnel ranging from 5,000 to 15,000 individuals and involving hundreds of subcontractors. Many of these fab construction projects demand completion from groundbreaking to operational handover within 8-10 months while fabs with the most advanced manufacturing process may take 12-18 months. These need the coordination and integration skills of construction engineers and project manager fostered in civil engineering to ensure the holistic achievement of safety, quality, value, and timely completion.
It is well recognized that the rapid advancements in Information Technology (IT) have made CAD (Computer Aided Design) techniques extensively applicable across various fields. The adoption of 3D CAD, combined with object-oriented, parametric, and relational design, forms the basis of Building Information Modeling (BIM). BIM is extensively used throughout the lifecycle of facility construction, including planning, design, procurement, construction, handover, maintenance, and operation. The ability of digitally draft and simulate building projects in 3D enhances the interdisciplinary design, review, and communication processes. The computer aided group in civil engineering realized the enhancement.
Traditional civil engineering has applied the principles, techniques, and methods of civil engineering to general civil infrastructure projects such as houses, buildings, roads, railways, bridges, harbors, dams, airports, etc. In the context of semiconductor chips manufacturing facilities, civil engineering applies its diverse academic specialties to the construction and operation of high-tech fab facility projects. The establishment of these fab facilities is an indispensable link in the semiconductor
chips manufacturing process of high-tech industries. It requires a significant number of civil engineering professionals to actively participate in the construction and operation of the necessary fab facilities.
土木工程在半導體製造中的角色[1、2、5、6]：
眾所皆知，在資訊科技突飛猛進的時代，不論在那個高科技產業，其背後所需之核心產品就是半導體，用半導體製作出來的晶片，將細緻複雜的軟體程式連結，最後啟動使用端高科技產品之應用，如機器人、物聯網、大數據、雲計算、虛擬現實 (VR)、人工智能 (AI) 等等。半導體是高科技產業成長繁榮的基本糧食。
綜觀高科技半導體晶片的製造和進一步的研發過程中，必須運用高效能的製造設備(Tools)、精準敏銳的儀器(Instrument)和超純淨的水、電、空氣、化學原料等等的廠房公用設施(Utilities)，同樣地，而這些研發製造程序必須在嚴格控制的潔淨無塵室中，穩定的製造平臺上,及/或沒有在電磁波干擾的環境下進行。
這些製造設備、精密儀器與公用設施、都要擺放或架設在土木工程的土壤結構上，要土壤結構穩固，則須解決因地震、噪音、電磁波 (EMI)、射頻 (RF)、氣流、機臺共振等等所衍生的振動問題，以上皆需要土木工程裡的結構、大地工程專家來協助。
而生產所需之水、空氣和化學物之淨化，其廢水、廢氣、廢化學液之處理和回收再生、節能減碳以及環境生態之保護，樣樣都與土木的水利工程及環境工程有關。
而在新世代無人的高科技半導體晶片製造，製做程序可能高達數百道，生產機臺間，其原料、半成品、成品之有軌道、無軌道的自動輸送系統 (Automated Materials Handling System, AMHS) 路徑選擇和等侯時間之最佳化(Optimization & Queuing)，也需土木交通工程來將之最佳化。
又因奈米科技之提昇，發現這些小原子和原子叢粒子跟同型原子成份堆積而成的大型材料有顯著完全不同的特質。當這些粒子大小尺寸變小，其比表面積卻變大，這樣比表面積變大卻對該材料的化學及物理行為有非常大的影響，因此而改變了材料的顏色、表面反應性、光學性、磁性、機械性、熱力性、催化性、或生物性的各種特性，半導體晶片內電晶體之線寬已進入低於2奈米的製程，如何將先進奈米材料研發應用成土木材料亦是刻不容緩的課題。而奈米層級的製造，其廠房設施在興建營運上之空間資訊要求嚴謹，必須精準明確，土木工程的測量及空間資訊工程亦責無傍代。
另外，一座約1仟~3仟億臺幣的高科技半導體晶片製造廠房(先進製程的廠房可能要高達5千億以上) ，其施工人員可從5千至1萬5千人左右，協力廠家上百，要求從破土到蓋好驗收，在8~10月完成並移交給生產端去安裝機臺，這些更需土木之營建工程與專案管理人員來整合協調，在安全至上，最佳價值之成本考量下，如質如期完成。
眾所皆知，資訊科技 (Information Technology，簡稱IT) 進步神速，CAD (Computer Aided Design，電腦輔助設計) 技術已廣泛地被運用於各領域。以3D CAD加上物件導向 (Object Oriented)、參數化設計 (Parameter Design) 及關聯性 (Relationship) 所形成的建築資訊模型及模擬 (Building Information Modeling，簡稱BIM)，正被廣泛應用於各種廠房建築的整個生命週期過程中。半導體晶片製造廠房的規劃、設計、採購、施工、移交、維修到營運，三維度物件(3D Object) ，可以藉由電腦輔助設計來製圖、模擬，促進土木工程進行跨領域之平行設計、審定及溝通。
傳統的土木工程是將土木工程中的大地、結構、水利、環境、交通、營建管理、電腦輔助、測量與空間資訊、土木材料等學術專業之原理、技術、方法應用到一般土木營造，譬如：房屋、大廈、公路、鐵路、橋梁、隧道、港灣、水壩、機場等等公共設施。在半導體晶片製造廠房設施中的土木工程，則是將土木工程中各學術專業領域之原理、技術、方法應用到高科技廠房設施之興建營運工程上。要生產製造必先有廠房，高科技廠房工程涵蓋廠房設施的規劃、設計、採購、施工、移交、維修及經營管理等等議題，是高科技產業生產製造過程中不可或缺的重要環節之一，需要許多土木工程人才來積極參與半導體晶片製造所需的廠房設施之興建營運。
The Trend of Semiconductor Chips Manufacturing
As the above mentioned, Civil Engineering plays the indispensable role in the manufacturing of semiconductor chips and further research and development. In semiconductor chips manufacturing, as the gate length of each transistor in chips is scaling down from 22nm to 14nm, to 10nm, and further down to 2nm and below, it not only enhances the speed and quantity of digital information transmission but also significantly reduces the energy and materials required, providing undeniable competitive advantages in performance and cost. [3]
Hence, the global race in semiconductor chips manufacturing is not only about pushing the limits of how small gate lengths can be engineered, but also, about achieving high yield with the capacity of making massive production. It is well known, during the recent global pandemic, the lack of semiconductor chips resulted from supply chain disruptions. It led to significant production delays for major automakers like Tesla, GM, Ford, John Deere, Toyota, Honda, BMW, and Volvo.
This situation underscored the critical need for high-yield massive production. These also demonstrated that the importance, not only scaling down the gate lengths to smaller, but also, being produced in large quantities with high yielding rate.
However, to achieve high yielding in mass production of semiconductor chips is inherently dependent on the availability of sophisticated fab facilities. Thus, those with the most advanced and adequate semiconductor manufacturing plants will definitely hold a competitive edge. Taiwan, in particular, leads the global semiconductor chips manufacturing industry and has already entered high-yield mass production of 3nm transistor gate widths, setting industry example that others strive to emulate.
The close-knit relationship between various civil engineering disciplines and the essential infrastructure of fab facilities required for semiconductor chips manufacturing is undeniable. While looking at future trend, the R&D of the next-generation of semiconductor chips will be an intelligent heterogeneous integration which amalgamates AI, GPU, CPC, Memory and other smart functional components. That is a multi-disciplinary semiconductor product.
The supplemental fab facilities for the intelligent heterogeneous integration will likely involve even greater interdisciplinary collaboration, incorporating not only civil engineering but also fields such as architecture, mechanical engineering, chemical engineering, electrical engineering, physics, chemistry, biology, materials science, medicine, agriculture, ecology, law, management, economics, finance, humanities, and the arts.[4]
Simultaneously, it is crucial to recognize that to advance and to enhance semiconductor chips manufacturing technology, fab facilities are an indispensable prerequisite. Its chips manufacturing cannot proceed without these fab facilities. In other words, the fab facilities must be ready prior to the chips manufacturing.
The research and development of these fab facilities are also critical components in the manufacturing of semiconductor chips. Enhancing the manufacturing processes of semiconductor chips requires active cooperation in the research and development of fab facilities. This cannot be overlooked or treated lightly; proactive measures and keeping pace with technological advancements are necessary to accelerate the R&D of fab facilities that timely, massively and high-yieldingly supplement the semiconductor chips manufacturing.
半導體晶片製造趨勢：
土木工程在半導體晶片製造和其進一層的研發裡扮演不可或缺的角色，半導體晶片製造中，將晶片裡每顆電晶體(Transistor) 的線寬(Gate Length)尺寸愈做愈小(Scaling Down)，從22nm, 14nm, 10nm, 7nm, 3nm, 2nm, 1.4nm, 1nm, 一直往下縮小到低於1nm…，不但有提升數位資訊傳輸的速度和數量，可以大量節省能源和材料之需求，而且擁有種種不可抗力的使用功能和成本的競爭優勢(Competitive Advantage of Performance and Cost)。[3]
因此，百家鳴放，爭先恐後地，不論將晶圓(Wafer)切割成一顆小米穀大小的小小晶片或乾脆製作一張等同晶圓尺寸大小，類似平板電腦(ipad)的晶片，都想要將每個晶片(Chip)裡的成億上兆之電晶體(Transistor)中的閘門線寬(Gate Length)尺寸，做到低於１奈米(nanometer) 。而今，要成功做好一顆、數顆、或一小批量低於一奈米，甚至低於0.1奈米閘門線寬的實驗室比比皆是，幾乎家家可以做到。
的確，晶片裡的閘門線寬，除了愈做愈小，是科技發展向前邁進之一條重要道路，同時晶片要能大量生產，良率又要高，也變得一樣重要，相信大家記憶猶新，前三年由於新冠病毒之肆虐，不知有多少Tesla、GM、Ford、John Deere、Toyota、Honda、BMW、Volvo的車子，因全球貿易戰導致供應鏈斷線、補給不足，成萬上億台的車輛沒有半導體晶片去驅動，不是擺在各處可停的停車場，就是靠在路邊閒放。如此，彰顯晶片裡的閘門線寬尺寸不僅要能愈做愈小，而且也要能在高良率下大量生產。
要在高良率下大量生產，其背後就是要靠是否有足夠的廠房設施之輔助功能才能辦得到，也就是說，誰有更多更好的晶圓晶片製造的廠房設施，誰的優勢就更多、競爭力就更強。
台灣廠家目前擁有世界上最多最好的半導體晶片製造工廠，在最先進之半導體晶片製造的激烈競賽下，全球領先，成為唯一己進入3奈米電晶體線寬之大量生產的矽島，其良率更讓所有競爭者，望塵莫及，並成為各家學習觀摩的典範。
誠如前述，土木工程之各學術專業領域與半導體晶片製造所必備有的廠房設施，有不可分割的緊密關係，也就是土木工程各領域(結構、大地、水利、環工、交通、測量空間資訊、營建、材料、電腦輔助)在半導體晶片製造中都有參與的重要角色。
下世代之半導體晶片製造所必須有的廠房工程，其研發創新應是更大的跨領域結合，除了土木工程各學術專業領域外，也應包括建築、機械、化工、電機、物理、化學、生物、材料、醫學、農工、生態、法律、管理、經濟、財務、人文、藝術等等各專業領域優秀的人才，來共同提昇半導體晶片製造所需之廠房設施。[4]
同時，希望大家謹記，要推進提昇半導體晶片製造技術，廠房設施是半導體晶片製造提昇中一個不可或缺的先決條件，即要製造，必先有廠房設施，而廠房設施之研究發展，亦是半導體晶片製造不可或缺的重要環節，提升半導體晶片之製程技術，廠房設施之研發亦應積極配合，不可等閒視之，必須未雨綢繆，與時俱進，加速研發。
1. http://www.ntuce-newsletter.tw/vol.90/T4_12.html
2. https://www.nvidia.com/gtc/keynote/
3. https://www.youtube.com/watch?v=87Gf5TFtRFU
4. Chang, Luh-Maan, "Engineering of High-Tech Facilities in the Nanotechnology Era," Journal of Civil and Hydraulic Engineering, Taipei, Taiwan, Vol. 35, No. 1, pp. 15-26, 2008.
5. 張陸滿。「土木工程在高科技廠房工程的角色」，土木水利，中國土木水利工程學會，臺北，臺灣，第46卷，第6期，第59-64頁，2019年12月。
6. Chang, Luh-Maan, “Roles of Civil Engineering in High-Tech Fab Engineering,” Bi-Monthly Magazine, Chinese Institute of Civil & Hydraulic Engineering, Volume 46, Issue 6, pp. 59-64, December 2019. (English version)
It is well understood that in the era of rapid technological advancement, semiconductors are the backbone of all high-tech industries. The chips produced using these semiconductors integrate intricate software programs and ultimately drive the high-tech devices we use, such as robots, the Internet of Things (IoT), big data, cloud computing, virtual reality (VR,) artificial intelligence (AI) and quantum computing.
In the complex manufacturing and further development processes of high-tech semiconductor chips, the use of high-performance manufacturing equipment, precision instruments, and ultra-pure water, electricity, air, and chemicals are necessary. These facilities must be hosted in cleanrooms with tightly controlled environments for ensuring stable manufacturing conditions free from vibration interference.
These sophisticated equipment and precision instruments must be installed on stable structural platforms provided by civil engineering. This includes addressing vibrations arising from earthquakes, noise, electromagnetic interference (EMI), radio frequency (RF) interference, airflow, and machine resonance, all of which require the expertise of structural and geotechnical engineers.
Moreover, the purification of water, air, and chemicals needed for production and the treatment and recycling of wastewater, exhaust gases, and waste chemicals involve energy conservation and carbon reduction, tying directly into the domain of civil engineering's hydraulic and environmental engineering.
In the new generation of unmanned high-tech semiconductor manufacturing, the processes might involve hundreds of steps. The transportation of materials and products between machines requires an optimized automated material handling system (AMHS), involving route selection and queuing optimization, which also falls under the purview of civil engineering's transportation engineering.
Furthermore, with advancements in nanotechnology, it's been discovered that particles at the nano-scale exhibit properties significantly different from their larger material counterparts. As these particles decrease in size, their surface area-to-volume ratio increases, which significantly affects their chemical and physical behaviors. This change impacts the material's color, surface reactivity, optical properties, magnetic
properties, mechanical strength, thermal behavior, catalytic activity, or biocompatibility. With semiconductor transistor line widths now entering processes below 2 nanometers, the urgent application of advanced nano-materials in civil engineering is a pressing matter.
Moreover, the construction and operation of high-tech semiconductor chips manufacturing facilities demand stringent spatial information requirements. The precise and defined spatial engineering provided by civil engineering is crucial for the successful execution of these projects. Surveyors and geospatial engineers in civil engineering discipline are duty bound.
Additionally, a high-tech semiconductor manufacturing facility, particularly those with advanced processing capabilities, may cost between one to three trillion Taiwanese dollars (approximately 30 to 90 billion USD), with construction personnel ranging from 5,000 to 15,000 individuals and involving hundreds of subcontractors. Many of these fab construction projects demand completion from groundbreaking to operational handover within 8-10 months while fabs with the most advanced manufacturing process may take 12-18 months. These need the coordination and integration skills of construction engineers and project manager fostered in civil engineering to ensure the holistic achievement of safety, quality, value, and timely completion.
It is well recognized that the rapid advancements in Information Technology (IT) have made CAD (Computer Aided Design) techniques extensively applicable across various fields. The adoption of 3D CAD, combined with object-oriented, parametric, and relational design, forms the basis of Building Information Modeling (BIM). BIM is extensively used throughout the lifecycle of facility construction, including planning, design, procurement, construction, handover, maintenance, and operation. The ability of digitally draft and simulate building projects in 3D enhances the interdisciplinary design, review, and communication processes. The computer aided group in civil engineering realized the enhancement.
Traditional civil engineering has applied the principles, techniques, and methods of civil engineering to general civil infrastructure projects such as houses, buildings, roads, railways, bridges, harbors, dams, airports, etc. In the context of semiconductor chips manufacturing facilities, civil engineering applies its diverse academic specialties to the construction and operation of high-tech fab facility projects. The establishment of these fab facilities is an indispensable link in the semiconductor
chips manufacturing process of high-tech industries. It requires a significant number of civil engineering professionals to actively participate in the construction and operation of the necessary fab facilities.
土木工程在半導體製造中的角色[1、2、5、6]：
眾所皆知，在資訊科技突飛猛進的時代，不論在那個高科技產業，其背後所需之核心產品就是半導體，用半導體製作出來的晶片，將細緻複雜的軟體程式連結，最後啟動使用端高科技產品之應用，如機器人、物聯網、大數據、雲計算、虛擬現實 (VR)、人工智能 (AI) 等等。半導體是高科技產業成長繁榮的基本糧食。
綜觀高科技半導體晶片的製造和進一步的研發過程中，必須運用高效能的製造設備(Tools)、精準敏銳的儀器(Instrument)和超純淨的水、電、空氣、化學原料等等的廠房公用設施(Utilities)，同樣地，而這些研發製造程序必須在嚴格控制的潔淨無塵室中，穩定的製造平臺上,及/或沒有在電磁波干擾的環境下進行。
這些製造設備、精密儀器與公用設施、都要擺放或架設在土木工程的土壤結構上，要土壤結構穩固，則須解決因地震、噪音、電磁波 (EMI)、射頻 (RF)、氣流、機臺共振等等所衍生的振動問題，以上皆需要土木工程裡的結構、大地工程專家來協助。
而生產所需之水、空氣和化學物之淨化，其廢水、廢氣、廢化學液之處理和回收再生、節能減碳以及環境生態之保護，樣樣都與土木的水利工程及環境工程有關。
而在新世代無人的高科技半導體晶片製造，製做程序可能高達數百道，生產機臺間，其原料、半成品、成品之有軌道、無軌道的自動輸送系統 (Automated Materials Handling System, AMHS) 路徑選擇和等侯時間之最佳化(Optimization & Queuing)，也需土木交通工程來將之最佳化。
又因奈米科技之提昇，發現這些小原子和原子叢粒子跟同型原子成份堆積而成的大型材料有顯著完全不同的特質。當這些粒子大小尺寸變小，其比表面積卻變大，這樣比表面積變大卻對該材料的化學及物理行為有非常大的影響，因此而改變了材料的顏色、表面反應性、光學性、磁性、機械性、熱力性、催化性、或生物性的各種特性，半導體晶片內電晶體之線寬已進入低於2奈米的製程，如何將先進奈米材料研發應用成土木材料亦是刻不容緩的課題。而奈米層級的製造，其廠房設施在興建營運上之空間資訊要求嚴謹，必須精準明確，土木工程的測量及空間資訊工程亦責無傍代。
另外，一座約1仟~3仟億臺幣的高科技半導體晶片製造廠房(先進製程的廠房可能要高達5千億以上) ，其施工人員可從5千至1萬5千人左右，協力廠家上百，要求從破土到蓋好驗收，在8~10月完成並移交給生產端去安裝機臺，這些更需土木之營建工程與專案管理人員來整合協調，在安全至上，最佳價值之成本考量下，如質如期完成。
眾所皆知，資訊科技 (Information Technology，簡稱IT) 進步神速，CAD (Computer Aided Design，電腦輔助設計) 技術已廣泛地被運用於各領域。以3D CAD加上物件導向 (Object Oriented)、參數化設計 (Parameter Design) 及關聯性 (Relationship) 所形成的建築資訊模型及模擬 (Building Information Modeling，簡稱BIM)，正被廣泛應用於各種廠房建築的整個生命週期過程中。半導體晶片製造廠房的規劃、設計、採購、施工、移交、維修到營運，三維度物件(3D Object) ，可以藉由電腦輔助設計來製圖、模擬，促進土木工程進行跨領域之平行設計、審定及溝通。
傳統的土木工程是將土木工程中的大地、結構、水利、環境、交通、營建管理、電腦輔助、測量與空間資訊、土木材料等學術專業之原理、技術、方法應用到一般土木營造，譬如：房屋、大廈、公路、鐵路、橋梁、隧道、港灣、水壩、機場等等公共設施。在半導體晶片製造廠房設施中的土木工程，則是將土木工程中各學術專業領域之原理、技術、方法應用到高科技廠房設施之興建營運工程上。要生產製造必先有廠房，高科技廠房工程涵蓋廠房設施的規劃、設計、採購、施工、移交、維修及經營管理等等議題，是高科技產業生產製造過程中不可或缺的重要環節之一，需要許多土木工程人才來積極參與半導體晶片製造所需的廠房設施之興建營運。
The Trend of Semiconductor Chips Manufacturing
As the above mentioned, Civil Engineering plays the indispensable role in the manufacturing of semiconductor chips and further research and development. In semiconductor chips manufacturing, as the gate length of each transistor in chips is scaling down from 22nm to 14nm, to 10nm, and further down to 2nm and below, it not only enhances the speed and quantity of digital information transmission but also significantly reduces the energy and materials required, providing undeniable competitive advantages in performance and cost. [3]
Hence, the global race in semiconductor chips manufacturing is not only about pushing the limits of how small gate lengths can be engineered, but also, about achieving high yield with the capacity of making massive production. It is well known, during the recent global pandemic, the lack of semiconductor chips resulted from supply chain disruptions. It led to significant production delays for major automakers like Tesla, GM, Ford, John Deere, Toyota, Honda, BMW, and Volvo.
This situation underscored the critical need for high-yield massive production. These also demonstrated that the importance, not only scaling down the gate lengths to smaller, but also, being produced in large quantities with high yielding rate.
However, to achieve high yielding in mass production of semiconductor chips is inherently dependent on the availability of sophisticated fab facilities. Thus, those with the most advanced and adequate semiconductor manufacturing plants will definitely hold a competitive edge. Taiwan, in particular, leads the global semiconductor chips manufacturing industry and has already entered high-yield mass production of 3nm transistor gate widths, setting industry example that others strive to emulate.
The close-knit relationship between various civil engineering disciplines and the essential infrastructure of fab facilities required for semiconductor chips manufacturing is undeniable. While looking at future trend, the R&D of the next-generation of semiconductor chips will be an intelligent heterogeneous integration which amalgamates AI, GPU, CPC, Memory and other smart functional components. That is a multi-disciplinary semiconductor product.
The supplemental fab facilities for the intelligent heterogeneous integration will likely involve even greater interdisciplinary collaboration, incorporating not only civil engineering but also fields such as architecture, mechanical engineering, chemical engineering, electrical engineering, physics, chemistry, biology, materials science, medicine, agriculture, ecology, law, management, economics, finance, humanities, and the arts.[4]
Simultaneously, it is crucial to recognize that to advance and to enhance semiconductor chips manufacturing technology, fab facilities are an indispensable prerequisite. Its chips manufacturing cannot proceed without these fab facilities. In other words, the fab facilities must be ready prior to the chips manufacturing.
The research and development of these fab facilities are also critical components in the manufacturing of semiconductor chips. Enhancing the manufacturing processes of semiconductor chips requires active cooperation in the research and development of fab facilities. This cannot be overlooked or treated lightly; proactive measures and keeping pace with technological advancements are necessary to accelerate the R&D of fab facilities that timely, massively and high-yieldingly supplement the semiconductor chips manufacturing.
半導體晶片製造趨勢：
土木工程在半導體晶片製造和其進一層的研發裡扮演不可或缺的角色，半導體晶片製造中，將晶片裡每顆電晶體(Transistor) 的線寬(Gate Length)尺寸愈做愈小(Scaling Down)，從22nm, 14nm, 10nm, 7nm, 3nm, 2nm, 1.4nm, 1nm, 一直往下縮小到低於1nm…，不但有提升數位資訊傳輸的速度和數量，可以大量節省能源和材料之需求，而且擁有種種不可抗力的使用功能和成本的競爭優勢(Competitive Advantage of Performance and Cost)。[3]
因此，百家鳴放，爭先恐後地，不論將晶圓(Wafer)切割成一顆小米穀大小的小小晶片或乾脆製作一張等同晶圓尺寸大小，類似平板電腦(ipad)的晶片，都想要將每個晶片(Chip)裡的成億上兆之電晶體(Transistor)中的閘門線寬(Gate Length)尺寸，做到低於１奈米(nanometer) 。而今，要成功做好一顆、數顆、或一小批量低於一奈米，甚至低於0.1奈米閘門線寬的實驗室比比皆是，幾乎家家可以做到。
的確，晶片裡的閘門線寬，除了愈做愈小，是科技發展向前邁進之一條重要道路，同時晶片要能大量生產，良率又要高，也變得一樣重要，相信大家記憶猶新，前三年由於新冠病毒之肆虐，不知有多少Tesla、GM、Ford、John Deere、Toyota、Honda、BMW、Volvo的車子，因全球貿易戰導致供應鏈斷線、補給不足，成萬上億台的車輛沒有半導體晶片去驅動，不是擺在各處可停的停車場，就是靠在路邊閒放。如此，彰顯晶片裡的閘門線寬尺寸不僅要能愈做愈小，而且也要能在高良率下大量生產。
要在高良率下大量生產，其背後就是要靠是否有足夠的廠房設施之輔助功能才能辦得到，也就是說，誰有更多更好的晶圓晶片製造的廠房設施，誰的優勢就更多、競爭力就更強。
台灣廠家目前擁有世界上最多最好的半導體晶片製造工廠，在最先進之半導體晶片製造的激烈競賽下，全球領先，成為唯一己進入3奈米電晶體線寬之大量生產的矽島，其良率更讓所有競爭者，望塵莫及，並成為各家學習觀摩的典範。
誠如前述，土木工程之各學術專業領域與半導體晶片製造所必備有的廠房設施，有不可分割的緊密關係，也就是土木工程各領域(結構、大地、水利、環工、交通、測量空間資訊、營建、材料、電腦輔助)在半導體晶片製造中都有參與的重要角色。
下世代之半導體晶片製造所必須有的廠房工程，其研發創新應是更大的跨領域結合，除了土木工程各學術專業領域外，也應包括建築、機械、化工、電機、物理、化學、生物、材料、醫學、農工、生態、法律、管理、經濟、財務、人文、藝術等等各專業領域優秀的人才，來共同提昇半導體晶片製造所需之廠房設施。[4]
同時，希望大家謹記，要推進提昇半導體晶片製造技術，廠房設施是半導體晶片製造提昇中一個不可或缺的先決條件，即要製造，必先有廠房設施，而廠房設施之研究發展，亦是半導體晶片製造不可或缺的重要環節，提升半導體晶片之製程技術，廠房設施之研發亦應積極配合，不可等閒視之，必須未雨綢繆，與時俱進，加速研發。
1. http://www.ntuce-newsletter.tw/vol.90/T4_12.html
2. https://www.nvidia.com/gtc/keynote/
3. https://www.youtube.com/watch?v=87Gf5TFtRFU
4. Chang, Luh-Maan, "Engineering of High-Tech Facilities in the Nanotechnology Era," Journal of Civil and Hydraulic Engineering, Taipei, Taiwan, Vol. 35, No. 1, pp. 15-26, 2008.
5. 張陸滿。「土木工程在高科技廠房工程的角色」，土木水利，中國土木水利工程學會，臺北，臺灣，第46卷，第6期，第59-64頁，2019年12月。
6. Chang, Luh-Maan, “Roles of Civil Engineering in High-Tech Fab Engineering,” Bi-Monthly Magazine, Chinese Institute of Civil & Hydraulic Engineering, Volume 46, Issue 6, pp. 59-64, December 2019. (English version)